System on chip (SoC) is an integrated circuit (IC) that integrates all components of a computer or other electronic system into a single chip. In the formation of a stacked SoC wafer, devices and logic circuits can be formed on separate silicon substrates or different wafers, followed by the formation of an interconnect structure on one side of a silicon chip. SoC wafer can be bonded to a read-out chip through metal-to-metal bonding or a hybrid bonding, and the read-out chip is further bonded to peripheral circuit chip, which may be an Application Specific Integrated Circuit (ASIC) chip. Peripheral circuit chip may include Image Signal Processing (ISP) circuits, and may, or may not, further include other circuits that are related to the SoC applications. The bonding of chips may be at wafer level. In the wafer-level bonding, individual wafers are bonded together, and are then sawed into dies. Alternatively, the bonding may be performed at the chip level.
The formation of the interconnect structure in the stacked SoC wafer is used to electrically connect the electrical components in different level of wafers stacked together, and the depth of the interconnect structure is substantially greater than those not in a stacked wafer system. Interconnect structure includes dielectric layers, metal lines and metal vias. Interconnect structure may include a plurality of metal layers. Dielectric layers may include low-k dielectric layers and possibly a passivation layer(s) over the low-k dielectric layers. The low-k dielectric layers have low k values, for example, lower than about 3.0. The passivation layer may be formed of a non-low-k dielectric material having a k value greater than 3.9.